Novel fabrication process to realize ultra-thin (EOT=0.7nm) and ultra-low leakage SiON gate dielectrics

被引：0

作者：

Matsushita, D ^{[1
]}

Muraoka, K ^{[1
]}

Nakasaki, Y ^{[1
]}

Kato, K ^{[1
]}

Inumiya, S ^{[1
]}

Eguchi, K ^{[1
]}

Takayanagi, M ^{[1
]}

机构：

[1] Toshiba Co Ltd, Adv LSI Technol Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

N Si-3; SiON; roughness; thin EOT; low leakage current; gate dielectrics;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We achieved 0.73 nm EOT, 88 A/cm(2) J(g), and 92% G(m) of that for SiO2 by just oxidation of SiN films. In addition, we achieved further improvement of EOT-J(g) characteristics by re-nitridation process with minimum degradation of G(m). EOT of 0.70 nm and J(g) as 95 A/cm(2) is realized with superior suppression of boron penetration (DeltaV(th) = 0.04 V).

引用

页码：172 / 173

页数：2

共 4 条

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2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, :202-203

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