Placement and routing for performance-oriented FPGA layout

被引：5
作者：
Alexander, MJ [1 ]
Cohoon, JP
Ganley, JL
Robins, G
机构：
[1] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99164 USA
[2] Univ Virginia, Dept Comp Sci, Charlottesville, VA 22903 USA
[3] Cadence Design Syst Inc, San Jose, CA 95134 USA
来源：
VLSI DESIGN | 1998年 / 7卷 / 01期
关键词：
FPGAs; placement; routing; performance-driven layout; Steiner trees; arborescences; multi-weighted graphs;
D O I：
10.1155/1998/38483
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.
引用
收藏
页码：97 / 110
页数：14
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