Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra

被引：0
|
作者：
Srimani, Supriyo [1 ]
Kundu, Diptendu Kumar [2 ]
Panda, Saradindu [3 ]
Maji, B. [4 ]
机构：
[1] Rajabazar Sci Coll, Dept Radio Phys & Elect, Kolkata, India
[2] Narula Inst Technol, Elect & Telecommun Dept, Kolkata, India
[3] Narula Inst Technol, ECE Dept, Kolkata, India
[4] Natl Inst Technol, ECE Dept, Durgapur, India
来源：
COMPUTATIONAL ADVANCEMENT IN COMMUNICATION CIRCUITS AND SYSTEMS, ICCACCS 2014 | 2015年 / 335卷
关键词：
DSP; Vedic mathematics; Vedic multiplier;
D O I：
10.1007/978-81-322-2274-3_49
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Digital signal processing (DSP) operations are very important part of engineering as well as medical discipline. Designing of DSP operations have many approaches. For the designing of DSP operations, multiplication plays a important role to perform signal processing operations such as convolution and correlation. The aim of this paper is to design a multiplier circuit based on Vedic sutras and method for DSP operations based on ancient Vedic mathematics is contemplated. In this paper, we have given the design up to multipliers based on Vedic multiplication sutra 'Urdhva-Tiryakbhyam' the design of 4 x 4 has been sketched in DSCH2 and all the outputs have been given. The layout of those circuits has also been generated by Microwind. The internal circuit diagram of all the blocks has been explained. The noise power have been calculated by T-Spice-13 in 45 nm Technology. This algorithm is implemented in MATLAB and also compared with the inbuilt functions in MATLAB.
引用
收藏
页码：443 / 449
页数：7
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