On SRAM Bit-Cells Once Again

被引：0
作者：
Tache, Mihai [1 ]
Kharbash, Fekri [1 ]
Beiu, Valeriu [1 ]
机构：
[1] United Arab Emirates Univ, Coll Informat Technol, POB 15551, Al Ain, U Arab Emirates
来源：
2014 10TH INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION TECHNOLOGY (IIT) | 2014年
关键词：
CMOS; SRAM; transistor sizing; static noise margin (SNM); reliability; NOISE MARGIN; DESIGN; LENGTH;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Noises and variations are ubiquitous, but are still being ill-understood and in most cases treated simplistically, leading in most cases to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to ultra-low voltage (ULV) SRAM cells. We will show that unconventionally sized SRAM cells achieve higher SNM's than classically sized SRAM cells (hence it is to be expected that they will work correctly at lower supply voltages).
引用
收藏
页码：80 / 83
页数：4
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