A 10-Gb/s inductorless CMOS limiting amplifier with third-order interleaving active feedback

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mu m CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 2(31) - 1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10(-12) are 300 and 10 mV(PP), respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68 x 0.8 mm(2) where the active circuit area only occupies 0.32 x 0.6 mm(2).