Enabling VirtIO Driver Support on FPGAs

被引:7
作者
Bandara, Sahan [1 ]
Sanaullah, Ahmed [2 ]
Tahir, Zaid [1 ]
Drepper, Ulrich [2 ]
Herbordt, Martin [1 ]
机构
[1] Boston Univ, CAAD Lab, ECE Dept, Boston, MA 02215 USA
[2] Red Hat Inc, Raleigh, NC USA
来源
2022 IEEE/ACM INTERNATIONAL WORKSHOP ON HETEROGENEOUS HIGH-PERFORMANCE RECONFIGURABLE COMPUTING (H2RC) | 2022年
关键词
FPGA; PCIe; VirtIO;
D O I
10.1109/H2RC56700.2022.00006
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Host-FPGA connectivity is critical for enabling a vast number of FPGA use cases in data centers, edge, and IoT. This interface must be reliable, robust, and uniform, whilst supporting necessary protocols and functionality. However, existing support for host-FPGA connectivity has several drawbacks on both the host and the device. This includes a lack of portability and poor upstream support, both of which can make it difficult for CPUs to easily and effectively leverage FPGAs. Native VirtIO drivers in the host operating system can help address some of these limitations, especially on the host side, but implementing device-side support for the VirtIO specification is a challenge due to the substantial hardware complexity involved. In this work, we present a framework for enabling FPGAs to interface native operating system VirtIO drivers on the host. To reduce the implementation overhead and improve portability, this framework uses both generic RTL blocks and modified, chip/device specific PCIe IP blocks. Moreover, this approach implements all the necessary data structures and functionality needed to meet the VirtIO specification requirements. We test the framework using the Xilinx DMA/Bridge Subsystem for PCI Express (XDMA) IP, implemented on an Alinx AX7A200 FPGA board (with a Xilinx XC7A200TFBG484-2 FPGA chip), and a host machine running the Fedora operating system. Our results show that the FPGA can be successfully enumerated as a VirtIO device, and interfaced using only native Linux VirtIO drivers.
引用
收藏
页码:1 / 8
页数:8
相关论文
共 22 条
[1]  
[Anonymous], 2010, PCI Express Base Specification Revision 3.0
[2]  
[Anonymous], 2020, 7 SER FPGAS INT BLOC
[3]   The Future of FPGA Acceleration in Datacenters and the Cloud [J].
Bobda, Christophe ;
Mbongue, Joel Mandebi ;
Chow, Paul ;
Ewais, Mohammad ;
Tarafdar, Naif ;
Vega, Juan Camilo ;
Eguro, Ken ;
Koch, Dirk ;
Handagala, Suranga ;
Leeser, Miriam ;
Herbordt, Martin ;
Shahzad, Hafsah ;
Hofste, Peter ;
Ringlein, Burkhard ;
Szefer, Jakub ;
Sanaullah, Ahmed ;
Tessier, Russell .
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2022, 15 (03)
[4]  
Caulfield AM, 2016, INT SYMP MICROARCH
[5]   A Framework for Neural Network Inference on FPGA-Centric SmartNICs [J].
Guo, Anqi ;
Geng, Tong ;
Zhang, Yongan ;
Haghi, Pouya ;
Wu, Chunshu ;
Tan, Cheng ;
Lin, Yingyan ;
Li, Ang ;
Herbordt, Martin .
2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2022, :430-437
[6]   Reconfigurable switches for high performance and flexible MPI collectives [J].
Haghi, Pouya ;
Guo, Anqi ;
Xiong, Qingqing ;
Yang, Chen ;
Geng, Tong ;
Broaddus, Justin T. ;
Marshall, Ryan ;
Schafer, Derek ;
Skjellum, Anthony ;
Herbordt, Martin C. .
CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2022, 34 (06)
[7]   FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid Solvers [J].
Haghi, Pouya ;
Geng, Tong ;
Guo, Anqi ;
Wang, Tianqi ;
Herbordt, Martin .
28TH IEEE INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2020, :148-156
[8]   Configurable Network Protocol Accelerator (COPA) [J].
Krishnan, Venkata ;
Serres, Olivier ;
Blocksome, Michael .
IEEE MICRO, 2021, 41 (01) :8-14
[9]   Toward FPGA-Based HPC: Advancing Interconnect Technologies [J].
Lant, Joshua ;
Navaridas, Javier ;
Lujan, Mikel ;
Goodacre, John .
IEEE MICRO, 2020, 40 (01) :25-34
[10]  
Luebbers Enno., Simplify Software Integration for FPGA Accelerators with OPAE