A parallel implementation of LMS adaptive filter in hardware for landmine detection

Due to the sequential nature of software implementations of the least mean square (LMS) algorithm for processing ground penetrating radar (GPR) signals for landmine detection on uni-processor computers, search area coverage rates are lower than operational needs demand. Since hardware implementations can achieve concurrent execution through parallelization of computational elements, the penalty on execution speed due to sequential execution can be ameliorated. This paper describes a hardware implementation of LMS in a field programmable gate array (FPGA) based on a fully parallel and regular computing architecture. The architecture presented is designed specifically for data collected utilizing the NIITEK Ground Penetrating Radar (GPR), however, due to the regular architecture, this design can be easily modified to suit other sensor data formats. This paper also demonstrates quantitatively the increase in throughput achieved by an implementation on a reconfigurable FPGA compared to the same implementation in sequential software. Finally, we address how reconfigurable hardware can be integrated into an existing detection system. Here, computationally intensive tasks are scheduled to execute on hardware, thereby freeing up a processor to perform other scheduled tasks. This is achieved by embedding field programmable gate array (FPGA) board specific host-to-FPGA application programmer interface (API) calls into an existing software detection system.