fT-Integrator in digital CMOS process for continuous-time ΣΔ modulator

The f(T)-integration technique is further investigated through the use of pnp transistors commonly available in a mainstream digital CMOS process. Both lateral and vertical pnps have been employed in f(T)-integrator design. The integrator is used as a building block for a single-bit second-order lowpass continuous-time SigmaDelta modulator. The modulator prototype is fabricated in a digital 0.8mum CMOS technology and the measured results clearly confirm functionality of the proposed concept. The modulator chip operates at 320MHz clock speed from 3V supply with a maximum SNDR of 32dB and 38dB dynamic range for 4MHz signal bandwidth (OSR=40).