A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SEDR

被引：18

作者：

Kim, Taewoong ^{[1
]}

Chae, Youngcheol ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul, South Korea

来源：

2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2019年

关键词：

Buffer-embedded; noise-shaping; SAR ADC; input buffer; passive noise-shaping; data weighted averaging (DWA); mismatch error shaping (MES); DB SNDR; SFDR;

D O I：

10.1109/CICC.2019.8780230

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (C S ) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables C S value to be reduced, thus leading to significant power saving. An energy efficient 2 nd -order noise-shaping is realized using passive integrators with the C S and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.

引用

页数：4

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