Analysis and Simulation of Minimums of Short Circuit Ratio for Phase-Locked Loop Based Synchronization Stability of Parallel Connected Voltage Source Converters

It is a practical problem worth investigating that what minimums of the short circuit ratio (SCR) are when voltage source converters (VSC) can maintain their synchronization under given large disturbances without any short-circuit fault in grids. An overview of the synchronization stability is summarized through steady-state analysis. For a given disturbance, the minimum SCR can be provided through time domain simulation based on quasi-state large signal (QSLS) models, an equivalent current source model and a switching model, respectively. The results from steady state analysis and time domain simulation are consistent and their corresponding error is reasonable. The minimum SCR resulted from steady state analysis can be regarded as the limit of minimum SCR. The QSLS model with current transients can be used to estimate practical minimum SCR with which VSC can maintain their synchronization under agreed disturbances.