Realizable reduction of RC networks

被引：23
作者：
Sheehan, Bernard N. [1 ]
机构：
[1] Mentor Graph Corp, Wilsonville, OR 97070 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2007年 / 26卷 / 08期
关键词：
interconnect modeling; model-order reduction (MOR); parasitic extraction; time-constant equilibration reduction (TICER);
D O I：
10.1109/TCAD.2007.891374
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we develop from various points of view the TIme-Constant Equilibration Reduction (TICER) algorithm, a circuit-reduction method that converts a given RC network into a smaller RC network (one with fewer nodes and branches) by eliminating nodes that have few neighbors and small nodal time constants. Advantages of TICER include: great efficiency, intuitive error control, preservation of sparsity, output in the form of an RC network, and the ability to handle networks with many ports.
引用
收藏
页码：1393 / 1407
页数：15
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