Survey and evaluation of low-power full-adder cells

被引：0
作者：
Sayed, A [1 ]
Al-Asaad, H [1 ]
机构：
[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
来源：
ESA'04 & VLSI'04, PROCEEDINGS | 2004年
关键词：
full-adder cell design; low-power circuits; power and delay estimation; VLSI implementations;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we survey, various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments that compare the surveyed full-adder cells. The experiments simulate all combinations of input transitions and consequently determine the delay and power consumption for the various full-adder cells. Moreover, the simulation results highlight the weaknesses and the strengths of the various full-adder cell designs.
引用
收藏
页码：332 / 338
页数：7
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