di/dt noise in CMOS integrated circuits

被引：51
作者：
Larsson, P
机构：
[1] Bell Laboratories,
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 1997年 / 14卷 / 1-2期
关键词：
ground bounce; di/dt noise; simultaneous switching noise; low-noise design;
D O I：
10.1023/A:1008255029409
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This is an overview paper presenting di/dt noise from a designer's perspective. Analysis and circuit design techniques are presented taking package parasitics into account. The main focus is on digital CMOS design, but analysis and design suggestions can easily be extended to mixed-mode design.
引用
收藏
页码：113 / 129
页数：17
相关论文
共 70 条
[1]   FOLDED SOURCE-COUPLED LOGIC VS CMOS STATIC LOGIC FOR LOW-NOISE MIXED-SIGNAL ICS [J].
ALLSTOT, DJ ;
CHEE, SH ;
KIAEI, S ;
SHRIVASTAWA, M .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1993, 40 (09) :553-563
[2]  
BAKOGLU HB, 1990, INTERCONNECTIONS PAC
[3]   Noise computation in single chip packages [J].
Bathey, K ;
Swaminathan, M ;
Smith, LD ;
Cockerill, TJ .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1996, 19 (02) :350-360
[4]  
BECKER WD, 1995, IEEE 4 EL PERF EL PA, P24
[5]  
CHANDRAKASAN A, 1995, LOW POWER DIGITAL CM
[6]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[7]   HIGH-SPEED, LOW-SWITCHING NOISE CMOS MEMORY DATA OUTPUT BUFFER [J].
CHIOFFI, E ;
MALOBERTI, F ;
MARCHESI, G ;
TORELLI, G .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (11) :1359-1365
[8]  
COX DT, 1989, IEEE CUST INT CIRC C
[9]  
DENG AC, 1988, IEEE INT C COMP AID, P208
[10]   DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].
DENNARD, RH ;
GAENSSLEN, FH ;
YU, HN ;
RIDEOUT, VL ;
BASSOUS, E ;
LEBLANC, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268
1234567