An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process

This paper presents the design and simulation of a modified CMOS low noise amplifier (LNA) circuit in 180 nm CMOS standard technology. We modified a cascade LNA using pi model of capacitor circuit. Impedance matching network at the input of proposed circuit provides low noise figure (NF) and suitable gain at the operating frequency of 6 GHz. Obtained simulation results after extracting post layout (with total chip size 2500*1600 mu m(2)) provide higher gain (S-21) of 19.75 dB and noise figure of 1.14 dB. The reverse isolation (S-12) of the LNA is also achieved to - 30.8 dB. A comparison table confirms that the proposed LNA circuit has better performance than the other recent works.