A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture

被引:47
作者
Park, Jae-Woo [1 ]
Kim, Doogon [1 ]
Ok, Sunghwa [1 ]
Park, Jaebeom [1 ]
Kwon, Taeheui [1 ]
Lee, Hyunsoo [1 ]
Lim, Sungmook [1 ]
Jung, Sun-Young [1 ]
Choi, Hyeongjin [1 ]
Kang, Taikyu [1 ]
Park, Gwan [1 ]
Yang, Chul-Woo [1 ]
Choi, Jeong-Gil [1 ]
Ko, Gwihan [1 ]
Shin, Jaehyeon [1 ]
Yang, Ingon [1 ]
Nam, Junghoon [1 ]
Sohn, Hyeokchan [1 ]
Hong, Seok-In [1 ]
Jeong, Yohan [1 ]
Choi, Sung-Wook [1 ]
Choi, Changwoon [1 ]
Shin, Hyun-Soo [1 ]
Lim, Junyoun [1 ]
Youn, Dongkyu [1 ]
Nam, Sanghyuk [1 ]
Lee, Juyeab [1 ]
Ahn, Myungkyu [1 ]
Lee, Hoseok [1 ]
Lee, Seungpil [1 ]
Park, Jongmin [1 ]
Gwon, Kichang [1 ]
Jeong, Woopyo [1 ]
Choi, Jungdal [1 ]
Kim, Jinkook [1 ]
Jin, Kyo-Won [1 ]
机构
[1] SK Hynix Semicond, Ichon, South Korea
来源
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) | 2021年 / 64卷
关键词
D O I
10.1109/ISSCC42613.2021.9365809
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:422 / 423
页数:2
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