Testing the interconnect of RAM-based FPGAs

被引：96

作者：

Renovell, M

Portal, JM

Figueras, J

Zorian, Y

机构：

[1] Univ Montpellier 2, LIRMM, F-34392 Montpellier, France

[2] Univ Politecn Cataluna, Dept Elect, Barcelona, Spain

[3] LogicVis Inc, San Jose, CA USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1998年 / 15卷 / 01期

关键词：

D O I：

10.1109/54.655182

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

引用

页码：45 / 50

页数：6

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