Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal-Oxide-Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process

被引:4
作者
Park, Jae Hyun [1 ]
Song, Jae Young
Kim, Jong Pil
Kim, Sang Wan
Yun, Jang-Gn
Park, Byung-Gook
机构
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea
关键词
MOSFET; CMOS; DESIGN;
D O I
10.1143/JJAP.49.084203
中图分类号
O59 [应用物理学];
学科分类号
摘要
The silicon nanowire gate-all-around (GAA) metal-oxide-semiconductor field effect transistors (MOSFETs) have been fabricated by using inverted sidewall spacers to scale the gate length The patterning strategy of inverted sidewall spacers is based on the self-aligned local-channel V-shaped gate electrode (V-gate) by optical lithography (SALVO) process Through this technique, we have obtained an aggressively scaled gate length down to 10 nm regime In addition, the silicon nanowire structure with diameter of about 10 nm has been successfully formed by reducing of the local channel In the fabricated device, we have confirmed that it has excellent device characteristics in terms of the sub-threshold swing (SS), drain induced barrier lowering (DIBL), and low level of off-state leakage current in spite of the short-channel effect (SCE) (C) 2010 The Japan Society of Applied Physics
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页数:5
相关论文
共 25 条
[1]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[2]   RECESSED-CHANNEL STRUCTURE FOR FABRICATING ULTRATHIN SOI MOSFET WITH LOW SERIES RESISTANCE [J].
CHAN, MS ;
ASSADERAGHI, F ;
PARKE, SA ;
HU, CM ;
KO, PK .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (01) :22-24
[3]   Extremely scaled silicon nano-CMOS devices [J].
Chang, LL ;
Choi, YK ;
Ha, DW ;
Ranade, P ;
Xiong, SY ;
Bokor, J ;
Hu, CM ;
King, TJ .
PROCEEDINGS OF THE IEEE, 2003, 91 (11) :1860-1873
[4]   Fabrication of self-aligned 90-nm fully depleted SOICMOS SLOTFETs [J].
Chen, CK ;
Chen, CL ;
Gouker, PM ;
Wyatt, PW ;
Yost, DR ;
Burns, JA ;
Suntharalingam, V ;
Fritze, M ;
Keast, CL .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (07) :345-347
[5]   Nanoscale multi-line patterning using sidewall structure [J].
Chung, KH ;
Sung, SK ;
Kim, DH ;
Choi, WY ;
Lee, CA ;
Lee, JD ;
Park, BG .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2002, 41 (6B) :4410-4414
[6]   Multiple-gate SOI MOSFETs [J].
Colinge, JP .
SOLID-STATE ELECTRONICS, 2004, 48 (06) :897-905
[7]   Analysis of the parasitic S/D resistance in multiple-gate FETs [J].
Dixit, A ;
Kottantharayil, A ;
Collaert, N ;
Goodwin, M ;
Jurezak, M ;
De Meyer, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (06) :1132-1140
[8]  
Hwang C.-G., 2006, ELECT DEVICES M 2006, P1
[9]  
Jiang Y., 2008, 2008 Symposium on VLSI Technology, P34, DOI 10.1109/VLSIT.2008.4588553
[10]   Novel method for silicon quantum wire transistor fabrication [J].
Kedzierski, J ;
Bokor, J ;
Anderson, E .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1999, 17 (06) :3244-3247