A 1.2V High Band-Width Analog Multiplier in 0.18μm CMOS Technology

Analog multiplier is an important building block for many analog computational applications. In this paper, a new compact, low power structure and low voltage CMOS analog multiplier is proposed. The proposed structure incorporates a cross-coupled squarer circuit. The most important features of this topology are low power consumption and high band-width that makes it suitable for use in high frequency applications. All of these are implemented using a compact circuit. The circuit is designed and analyzed in 0.18 mu m CMOS process model and the key features like bandwidth and THD are extracted. Simulation results for the circuit with a 1.2V single supply show a very low power consumption and better band-width with respect to comparable structures. Copyright (C) 2010 Praise Worthy Prize S.r.l. - All rights reserved.