A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

被引：8

作者：

Jung, YJ ^{[1
]}

Lee, SW ^{[1
]}

Shim, D ^{[1
]}

Kim, W ^{[1
]}

Kim, CH ^{[1
]}

Cho, SI ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul, South Korea

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852848

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low jitter dual loop DLL with multiple VCDLs has been developed. This DLL whose locking range is 150-600MHz, allows unlimited phase shift without noise sensitivity issues. A built-in duty cycle corrector guarantees 50% duty cycle under severe transistor mismatch.

引用

页码：50 / 51

页数：2

共 5 条

[1] 2 NOVEL FULLY COMPLEMENTARY SELF-BIASED CMOS DIFFERENTIAL-AMPLIFIERS [J].