A hardware-efficient, multirate, digital channelized receiver architecture

An approach is presented to realizing a digital channelized receiver for signal intercept applications that provides a hardware efficient implementation of a uniform filter bank in which the number of filters K is greater than the decimation factor M. The proposed architecture allows simple channel arbitration logic to be used and provides reliable instantaneous frequency measurements, even in adjacent channel crossover regions. In the proposed implementation of the filter bank, K is related to M by K = FM where F is an integer. It is shown that the optimum selection of F allows the instantaneous frequency measurement to be made in the channel crossover region and the arbitration function to be based solely on the instantaneous frequency measurement. The development of a biter bank structure which combines the flexibility of the short-time Fourier transform (STFT) with the implementation efficiency of the polyphase filter bank decomposition, meeting these requirements and leading to a hardware-efficient implementation, is presented.