Crosstalk noise analysis of on-chip interconnects for ternary logic applications using FDTD

This paper presents the crosstalk induced performance analysis of ternary logic coupled on-chip interconnects using an efficient mathematical model, finite-difference time-domain (FDTD) method. The complete driver-interconnect-load structure is analyzed for the realistic analysis of interconnects. The interconnect line is modeled by the FDTD method and standard ternary inverter driver is modeled by considering the quantum confinement effects. The crosstalk effects of functional and dynamic are examined for various test cases to examine the proposed model robustness. The length of on-chip ternary interconnects is varied from 200 to 1200 mu m, the numerical computations are carried out using matrix laboratory (MATLAB). The obtained proposed model results are compared with the HSPICE for verification. The average error for measuring the delay during the in-phase and out-phase switching is observed to be less than 1%. For the estimation of noise peak voltage, the average error is less than 2%. Moreover, the proposed model is found to be time efficient than the HSPICE simulations.