Hybrid DPWM with digital delay-locked loop

被引：0

作者：

Yousefzadeh, Vahid ^{[1
]}

Takayama, Toru ^{[1
]}

Maksimovic, Dragan ^{[1
]}

机构：

[1] Univ Colorado, Colorado Power Elect Ctr, ECE Dept, Boulder, CO 80309 USA

来源：

PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON COMPUTERS IN POWER ELECTRONICS | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization.

引用

页码：142 / +

页数：2

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