Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology

被引：1

作者：

Inaba, S ^{[1
]}

Nagano, H ^{[1
]}

Miyano, K ^{[1
]}

Mizushima, I ^{[1
]}

Okayama, Y ^{[1
]}

Nakauchi, T ^{[1
]}

Ishimaru, K ^{[1
]}

Ishiuchi, H ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, SoC Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358783

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, AC performance of SODEL CMOS (1) is discussed, aiming for low power CMOS applications. Propagation delay time (,taupd) in SODEL CMOS has been improved up to 25% in five stacked nFET inverters, and about 30% better power-delay producthas been observed at same taupd, compared to conventional (conv.) bulk CMOS. In SRAM cell application of SODEL CMOS, high SNM of similar to 95 mV was observed at Vdd = 0.6 V. Smaller bitline delay is confirmed by SPICE simulations. Latch-up immunity for alpha-particle was found to be comparable to conv. bulk CMOS. Therefore, SODEL CMOS technology will give us better solution for low power SoC.

引用

页码：225 / 228

页数：4