CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

被引:72
作者
Chen, Zhiyu [1 ]
Yu, Zhanghao [1 ]
Jin, Qing [2 ]
He, Yan [1 ]
Wang, Jingyu [1 ]
Lin, Sheng [2 ]
Li, Dai [1 ]
Wang, Yanzhi [2 ]
Yang, Kaiyuan [1 ]
机构
[1] Rice Univ, Dept Elect & Comp Engn, Houston, TX 77005 USA
[2] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA
关键词
CMOS; convolutional neural networks (CNNs); deep learning accelerator; in-memory computation; mixed-signal computation; static random-access memory (SRAM); SRAM; MACRO; ACCELERATOR; COMPUTATION;
D O I
10.1109/JSSC.2021.3056447
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single 512 x 128 macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.
引用
收藏
页码:1924 / 1935
页数:12
相关论文
共 35 条
  • [11] C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing
    Jiang, Zhewei
    Yin, Shihui
    Seo, Jae-Sun
    Seok, Mingoo
    [J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2019, 2 (09): : 131 - 134
  • [12] A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
    Kang, Mingu
    Gonugondla, Sujan K.
    Patil, Ameya
    Shanbhag, Naresh R.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (02) : 642 - 655
  • [13] Khwa WS, 2018, ISSCC DIG TECH PAP I, P496, DOI 10.1109/ISSCC.2018.8310401
  • [14] ImageNet Classification with Deep Convolutional Neural Networks
    Krizhevsky, Alex
    Sutskever, Ilya
    Hinton, Geoffrey E.
    [J]. COMMUNICATIONS OF THE ACM, 2017, 60 (06) : 84 - 90
  • [15] Gradient-based learning applied to document recognition
    Lecun, Y
    Bottou, L
    Bengio, Y
    Haffner, P
    [J]. PROCEEDINGS OF THE IEEE, 1998, 86 (11) : 2278 - 2324
  • [16] A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
    Liu, Chun-Cheng
    Chang, Soon-Jyh
    Huang, Guan-Ying
    Lin, Ying-Zu
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (04) : 731 - 740
  • [17] Mingu Kang, 2014, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), P8326, DOI 10.1109/ICASSP.2014.6855225
  • [18] Okumura S, 2019, S VLSI TECH, pC248
  • [19] Park S, 2015, ISSCC DIG TECH PAP I, V58, P80, DOI 10.1109/ISSCC.2015.7062935
  • [20] XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
    Rastegari, Mohammad
    Ordonez, Vicente
    Redmon, Joseph
    Farhadi, Ali
    [J]. COMPUTER VISION - ECCV 2016, PT IV, 2016, 9908 : 525 - 542