Simulation of the neurodynamic system of working memory

被引：0
作者：
Klin'shov, V. V.
Shchapin, D. S.
Nekorkin, V. I.
机构：
来源：
JOURNAL OF COMMUNICATIONS TECHNOLOGY AND ELECTRONICS | 2010年 / 55卷 / 07期
基金：
俄罗斯基础研究基金会;
关键词：
Basic Element; Memory System; Dynamic Mode; Electronic Circuit; Oscillatory Signal;
D O I：
10.1134/S1064226910070065
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The electronic circuit of the basic element of a neurodynamic memory system has been developed and implemented. The dynamic modes of the circuit and its responses to different external signals have been investigated experimentally. The circuit under study is shown to have all dynamic properties required for the memory system. The experimental results agree with those obtained in the previous theoretical studies of the neurodynamic memory system.
引用
收藏
页码：759 / 764
页数：6
相关论文
共 40 条
  • [21] IMPLEMENTATION OF EXTENDED OPEN CORE PROTOCOL INTERFACE MEMORY SYSTEM USING Verilog HDL
    Varughese, Elina Rajan
    Antony, Rony P.
    [J]. 2013 INTERNATIONAL CONFERENCE ON GREEN COMPUTING, COMMUNICATION AND CONSERVATION OF ENERGY (ICGCE), 2013, : 130 - 135
  • [22] Adaptive correlated prefetch with large-scale hybrid memory system for stream processing
    Sung Min Lee
    Su-Kyung Yoon
    Jeong-Geun Kim
    Shin-Dug Kim
    [J]. The Journal of Supercomputing, 2018, 74 : 4746 - 4770
  • [23] ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism
    Lym, Sangkug
    Ha, Heonjae
    Kwon, Yongkee
    Chang, Chun-kai
    Kim, Jungrae
    Erez, Mattan
    [J]. 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2018, : 670 - 682
  • [24] The design of compressed memory system for depth data in 3D rendering processors
    Park, Woo-Chan
    Yoon, Duk-Ki
    Kim, Dong-Seok
    Kim, Hong-Sik
    Park, Jin-Hong
    Jeong, Woo-Nam
    Han, Tack-Don
    [J]. IEICE ELECTRONICS EXPRESS, 2010, 7 (21): : 1622 - 1628
  • [25] Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing
    Zhang, Xinyue
    Wang, Yuan
    Zhang, Yawen
    Song, Jiahao
    Zhang, Zuodong
    Cheng, Kaili
    Wang, Runsheng
    Huang, Ru
    [J]. 17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
  • [26] Adaptive correlated prefetch with large-scale hybrid memory system for stream processing
    Lee, Sung Min
    Yoon, Su-Kyung
    Kim, Jeong-Geun
    Kim, Shin-Dug
    [J]. JOURNAL OF SUPERCOMPUTING, 2018, 74 (09) : 4746 - 4770
  • [27] Parallelism analysis of memory system in single-chip VLIW video signal processors
    Wu, Z
    Wolf, W
    [J]. MULTIMEDIA HARDWARE ARCHITECTURES 1998, 1998, 3311 : 58 - 66
  • [28] A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling
    Meng, Hongyu
    Meng, Hongli
    Ding, Pengfei
    Wang, Mingxuan
    Wang, Donglin
    [J]. PROCEEDINGS OF 2018 IEEE 9TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS), 2018, : 912 - 915
  • [29] Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System
    Kim, Jeong-Geun
    Kim, Shin-Dug
    Yoon, Su-Kyung
    [J]. ELECTRONICS, 2020, 9 (12) : 1 - 14
  • [30] MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System
    Bahar Asgari
    Saibal Mukhopadhyay
    Sudhakar Yalamanchili
    [J]. Journal of Signal Processing Systems, 2021, 93 : 659 - 675
1234