Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.