Configurable 8T SRAM for Enbling in-Memory Computing

被引：0

作者：

Chen, Han-Chun ^{[1
]}

Li, Jin-Fu ^{[1
]}

Hsu, Chun-Lung ^{[2
]}

Sun, Chi-Tien ^{[2
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Taoyuan 320, Taiwan

[2] Ind Technol Res Inst, Informat & Commun Res Labs, Hsinchu 300, Taiwan

来源：

PROCEEDINGS OF 2019 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION ENGINEERING AND TECHNOLOGY (ICCET 2019) | 2019年

关键词：

in-memory computing; static random access memory; content addressable memory; computing architecture;

D O I：

10.1109/iccet.2019.8726871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8T SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18 mu m CMOS technology.

引用

页码：139 / 142

页数：4

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