Extraction technique of trap density at grain boundaries in polycrystalline-silicon thin-film transistors with device simulation

An extraction technique of trap density at grain boundaries (D-gb) in polycrystalline-silicon thin-film transistors with two-dimensional (2D) device simulation has been developed. The energy profile of D-gb can be extracted by repeatedly fitting a simulated current-voltage (I-V) characteristic to a measured I-V characteristic with the consideration of potential barriers at grain boundaries. Particularly in this study, the actual dependence of the energy profile of D-gb on the irradiated energy during excimer laser crystallization (F-x) is analyzed by varying F-x = 410, 420, and 430 mJ-cm(-2). It is found that D-gb definitely depends on F-x, whereas trap density at an oxide interface slightly depends on F-x. This is because the grain boundaries are formed during the excimer laser crystallization and not exposed to subsequent fabrication processes. This discussion becomes possible for the first time by precise extraction using the extraction technique with the 2D device simulation.