FIRST MERGED INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING
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1998年
关键词:
D O I:
10.1109/IPPS.1998.669933
中图分类号:
TP301 [理论、方法];
学科分类号:
081202 ;
摘要:
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm expressed in C source code is progressivly re-written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous systolic design.