A Low-Power Subthreshold Level Shifter in 180 nm Process

This paper proposes a power-efficient voltage level shifter architecture that is able to operate in the sub-threshold region. To avoid the static power dissipation, the proposed structure employs an auxiliary circuit to charge the internal nodes up to V-DDH. Moreover, the strength of the pull-down device is increased with the aid of a second auxiliary circuit. Post-layout simulation results of the proposed structure in a 0.18-mu m CMOS technology show that at the input low supply voltage of V-DDL=0.3 V and the high supply voltage of V-DDH=1.8 V, the level shifter presents a propagation delay of 46 ns, a static power dissipation of 230 pW, and an energy per transition of 84 fJ, when the frequency of the input signal is 1 MHz.