Chip-scale packaging of power devices and its application in integrated power electronics modules

被引:2
作者
Liu, XS [1 ]
Jing, XK [1 ]
Lu, GQ [1 ]
机构
[1] Virginia Tech, Ctr Power Elect Syst, Power Elect Packaging Lab, Blacksburg, VA 24061 USA
来源
50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS | 2000年
关键词
D O I
10.1109/ECTC.2000.853179
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional integrated power electronics modules (IPEMs). The chip-scale packaging structure, termed Die Dimensional Ball Grid Array (D(2)BGA), eliminates wire bonds by using stacked solder bumps to interconnect power chips. D(2)EGA package consists of a power chip, inner solder bumps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniature possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultra-low profile packaging. Electrical tests show that the V-CE(sat) and on-resistance of the D(2)BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device's wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D(2)BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.
引用
收藏
页码:370 / 377
页数:4
相关论文
共 24 条
[1]  
[Anonymous], MICROELECTRONICS PAC
[2]  
BINDRA A, 1999, ELECT DESIGN 0517, P52
[3]  
CLEMENTI J, 1993, P ELECTR C, P175, DOI 10.1109/ECTC.1993.346835
[4]  
ERICKSEN T, 1997, PCIM POWER ELECT I P
[5]  
Ferreira JA, 1997, APPL POWER ELECT CO, P419, DOI 10.1109/APEC.1997.581484
[6]  
FISHER R, 1995, APPL POWER ELECT CO, P12, DOI 10.1109/APEC.1995.468955
[7]  
GIBSON B, 1990, SURFACE MOUNT TECHNO, P23
[8]   An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures [J].
Haque, S ;
Xing, K ;
Lin, RL ;
Suchicital, CTA ;
Lu, GQ ;
Nelson, DJ ;
Borojevic, D ;
Lee, FC .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 1999, 22 (02) :136-144
[9]  
HO TH, 1995, ECTC, P930
[10]  
IACOB P, 1994, P INT S TEST FAIL AN, P319