FabCache: Cache Design Automation for Heterogeneous Multi-core Processors

Single-ISA heterogeneous multi-core architecture which consists of diverse superscalar cores is increasing importance in the processor architecture. Using a proper superscalar core for characteristic in a program contributes to reduce energy consumption and improve performance. However, designing a single-ISA heterogeneous multi-core processor requires a large design and verification effort which is multiplied by the number of different core types. In addition, cache systems for each superscalar core and a shared bus system to connect between differently-designed caches also cause increase in the design effort. In particular, a heterogeneous multi-core processor may have various cache structures, such as only L1 cache, L1 and unified L2 caches, L1 and dedicated L2 caches and each cache differs in cache dimensions, i.e., cache capacity, line size, and associativity. Therefore, we have proposed FabHetero to solve this problem. FabHetero is a framework to generate diverse heterogeneous multi-core processors automatically using FabScalar, FabCache, and FabBus which generate various designs of superscalar core, cache system, and flexible shared bus system, respectively. This paper presents the detail of FabCache. We show that the caches which have arbitrary parameters such as cache capacity, line size, associativity, access latency, and line transmission width between cache hierarchies generated by FabCache work correctly.