A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

被引：5

作者：

Hamamoto, T ^{[1
]}

Kawasaki, S ^{[1
]}

Furutani, K ^{[1
]}

Yasuda, K ^{[1
]}

Konishi, Y ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, ULSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852857

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：76 / 77

页数：2

共 3 条

[1]

Hongil Yoon, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), P412, DOI 10.1109/ISSCC.1999.759327

[2] A 2.5-V CMOS DELAY-LOCKED LOOP FOR AN 18-MBIT, 500-MEGABYTE/S DRAM [J].

LEE, TH ;

DONNELLY, KS ;

HO, JTC ;

ZERBE, J ;

JOHNSON, MG ;

ISHIKAWA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1491-1496

[3]

Yoshimura T., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P66, DOI 10.1109/VLSIC.1998.688006

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