Full Hardware Implementation of FreeRTOS-Based Real-Time Systems

被引:4
|
作者
Nakano, Wakako [1 ,3 ]
Shinohara, Yukino [1 ]
Ishiura, Nagisa [2 ]
机构
[1] Kwansei Gakuin Univ, Grad Sch Sci & Technol, 2-1 Gakuen, Sanda, Hyogo, Japan
[2] Kwansei Gakuin Univ, Sch Engn, 2-1 Gakuen, Sanda, Hyogo, Japan
[3] Hitachi Ltd, Tokyo, Japan
来源
2021 IEEE REGION 10 CONFERENCE (TENCON 2021) | 2021年
关键词
real-time systems; RTOS; FreeRTOS; hardware accelerator; system synthesis; high-level synthesis;
D O I
10.1109/TENCON54134.2021.9707328
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
As higher and higher functionalities are being implemented in embedded systems, it is becoming difficult to ensure their real-time performance. As one approach to enhancing response performance of RTOS-based systems, Oosako proposed a method for implementing both kernel objects and RTOS functionalities as hardware utilizing high-level synthesis, where TOPPERS/ASP3 was assumed as an RTOS. This paper extends this method to deal with systems based on FreeRTOS. In FreeRTOS, tasks can be generated either statically or dynamically, whose control data are managed in linked lists. We place restrictions that all the tasks are generated before scheduler starts so that we can keep the task control data in an array. Software timers are dealt with as tasks that have their own timers. We also present methods to implement dispatch disabling for mutual exclusion and a data queue for asynchronous data communication. We have implemented a hardware module from a reduced version of a demo program main full.c and TimerDemo.c bundled with FreeRTOS, which took less than 300 ns and 700 ns for task control and data queue operations, respectively.
引用
收藏
页码:435 / 440
页数:6
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