2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer

被引：0

作者：

Yang, WR ^{[1
]}

Cao, JL ^{[1
]}

Ran, F ^{[1
]}

Wang, J ^{[1
]}

机构：

[1] Shanghai Univ, Microelect Res Dev Ctr, Shanghai 200072, Peoples R China

来源：

2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-speed dual-modulus divide-by-32/33 prescaler has been developed in a 0.25 in CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25 in CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6 mA at input frequency of 2.5 GHz.

引用

页码：1547 / 1550

页数：4

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