Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

被引:7
作者
Singh, Kunal [1 ]
Kumar, Mirgender [1 ]
Goel, Ekta [1 ]
Singh, Balraj [1 ]
Dubey, Sarvesh [2 ]
Kumar, Sanjay [1 ]
Jit, Satyabrata [1 ]
机构
[1] Indian Inst Technol BHU, Dept Elect Engn, Varanasi 221005, Uttar Pradesh, India
[2] Shri Ramswaroop Mem Univ, Fac Elect & Commun Engn, Lucknow Deva Rd, Barabanki 225003, India
关键词
DG MOSFETs; ultra-shallow junction (USJ); straggle parameter; drain-induced barrier lowering (DIBL); short-channel effects (SCEs); gate underlap; loss of switching speed; SIMULATION; FINFET;
D O I
10.1007/s11664-015-4254-y
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper reports a new two-dimensional (2D) analytical model for the potential distribution and threshold voltage of the short-channel symmetric gate underlap ultrathin DG MOSFETs with a lateral Gaussian doping profile in the source (S)/drain (D) region. The parabolic approximation and conformal mapping techniques have been explored for solving the 2D Poisson's equation to obtain the channel potential function of the device. The effects of straggle parameter (of the lateral Gaussian doping profile in the S/D region), underlap length, gate length, channel thickness and oxide thickness on the surface potential and threshold voltage have been investigated. The loss of switching speed due to the drain-induced barrier lowering (DIBL) has also been reported. The proposed model results have been validated by comparing them with their corresponding TCAD simulation data obtained by using the commercially available 2D ATLAS (TM) simulation software.
引用
收藏
页码:2184 / 2192
页数:9
相关论文
共 22 条
[21]   3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual-material-gate (DMG) SOI FinFETs [J].
Saha, Rajesh ;
Baishya, Srimanta ;
Bhowmick, Brinda .
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2018, 17 (01) :153-162
[22]   Analytical Modeling of Threshold Voltage of Stacked Triple-Material-Gate (TMG) Strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs [J].
Santra, Abirmoya ;
Kumar, Mirgender ;
Dubey, Sarvesh ;
Jit, Satyabrata ;
Tiwari, Pramod Kumar .
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2014, 9 (2-3) :235-257