A novel CMOS full adder

被引：10

作者：

Navi, Keivan ^{[1
]}

Kavehie, Omid ^{[1
]}

Rouholamini, Mahnoush ^{[2
]}

Sahafi, Amir ^{[2
]}

Mehrabi, Shima ^{[2
]}

机构：

[1] Shahid Beheshti Univ Med Sci, Dept Elect & Comp Engn, Evin 19839-63113, Tehran, Iran

[2] Res & Sci Ctr Hesarak, Tehran, Iran

来源：

20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA | 2007年

关键词：

D O I：

10.1109/VLSID.2007.18

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a high-speed adder cell using a new design style called "bridge". The bridge design style offers more regularity and higher density than conventional CMOS design style, by using some transistors, named bridge transistors. Results show 4.4% (@ Vdd=3 volt) to 34.1% (@ Vdd=1 volt) improvement in speed over conventional CMOS adder. HSPICE is the circuit simulator used, and the technology being used for simulations is BSIM3v3 0.18 mu m technology.

引用

页码：303 / +

页数：3

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