A 2-D systolic array for high-throughput computation of 2-D discrete fourier transform

被引：0
|
作者：
Meher, P. K. [1 ]
Patra, J. C. [1 ]
Vinod, A. P. [1 ]
机构：
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
来源：
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年
关键词：
discrete Fourier transform (DFT); systolic array; digital signal processing (DSP) chip; VLSI;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A simple 2-dimensional architecture is derived for highly concurrent systolization of the 2-dimensional (2-D) discrete Fourier transform (DFT). The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N-point DFT is computed via four inner-products of real-valued data of length approximate to (N/2). The proposed structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the existing multiplier-based DFT structures.
引用
收藏
页码：1927 / +
页数：3
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