Towards High-Performance Polarity-Controllable FETs with 2D Materials

被引：0

作者：

Resta, Giovanni V. ^{[1
]}

Gonzalez, Jorge Romero ^{[3
]}

Balaji, Yashwanth ^{[2
]}

Agarwal, Tarun ^{[2
]}

Lin, Dennis ^{[2
]}

Catthor, Francky ^{[2
]}

Radu, Iuliana P. ^{[2
]}

De Micheli, Giovanni ^{[1
]}

Gaillardon, Pierre-Emmanuel ^{[3
]}

机构：

[1] Ecole Polytech Fed Lausanne, Integrated Syst Lab, Lausanne, Switzerland

[2] IMEC, Leuven, Belgium

[3] Univ Utah, Lab NanoIntegrated Syst, Salt Lake City, UT USA

来源：

PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | 2018年

基金：

美国国家科学基金会;

关键词：

DER-WAALS EPITAXY; LAYER MOS2; GROWTH; TECHNOLOGY;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

As scaling of conventional silicon-based electronics is reaching its ultimate limit, two-dimensional semiconducting materials of the transition-metal-dichalcogenides family, such as MoS2 and WSe2, are considered as viable candidates for next-generation electronic devices. Fully relying on electrostatic doping, polarity-controllable devices, that use additional gate terminals to modulate the Schottky barriers at source and drain, can strongly take advantages of 2D materials to achieve high on/off ratio and low leakage floor. Here, we provide an overview of the latest advances in 2D material processes and growth. Then, we report on the experimental demonstration of polarity-controllable devices fabricated on 2D-WSe2 and study the scaling trends of such devices using ballistic self-consistent quantum simulations. Finally, we discuss the circuit-level opportunities of such technology.

引用

页码：637 / 641

页数：5

共 39 条

[1] Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors
Amaru, Luca
Gaillardon, Pierre-Emmanuel
Zhang, Jian
De Micheli, Giovanni
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2013, 60 (10) : 672 - 676
[2] Ben Jamaa MH, 2009, DES AUT TEST EUROPE, P622
[3] Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
Borkar, S
[J]. IEEE MICRO, 2005, 25 (06) : 10 - 16
[4] 2D Semiconductor FETs-Projections and Design for Sub-10 nm VLSI
Cao, Wei
Kang, Jiahao
Sarkar, Deblina
Liu, Wei
Banerjee, Kaustav
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) : 3459 - 3469
[5] Cao W, 2013, PROC EUR S-STATE DEV, P37, DOI 10.1109/ESSDERC.2013.6818814
[6] Fiori G., 2009, IEEE IWCE 09, V09
[7] Fiori G, 2014, NAT NANOTECHNOL, V9, P768, DOI [10.1038/nnano.2014.207, 10.1038/NNANO.2014.207]
[8] Gaillardon P.-E., 2014, P C DES AUT TEST EUR
[9] Gao Y., 2016, NATURE COMMUNICATION, V6
[10] Van der Waals heterostructures
Geim, A. K.
Grigorieva, I. V.
[J]. NATURE, 2013, 499 (7459) : 419 - 425

← 1 2 3 4 →