On the phase noise of ΔΣ frequency discriminator for applications in frequency synthesizer

被引：0

作者：

Zheng, SF ^{[1
]}

Riley, TAD ^{[1
]}

Kostamovaara, J ^{[1
]}

机构：

[1] Univ Oulu, Dept Elect & Informat Engn, Oulu 90014, Finland

来源：

2004 INTERNATIONAL CONFERENCE ON COMMUNICATION, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEMS - VOL 2: SIGNAL PROCESSING, CIRCUITS AND SYSTEMS | 2004年

关键词：

delta-sigma; frequency modulation(FM); frequency discriminator; phase-locked loop; synthesizer;

D O I：

10.1109/ICCCAS.2004.1346383

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Phase noise analysis for the DeltaSigma frequency discriminator is presented in this paper, and a new architecture is proposed to improve the noise performance. This technique uses a mixer following the VCO to downconvert discriminator input from RF range to IF. It reduces the effect of N times in-band phase noise amplification, and relaxes the requirement of timing accuracy in a higher order DeltaSigma frequency discriminator. MATLAB simulation shows significant noise improvement in the presence of timing errors from logic devices.

引用

页码：1170 / 1173

页数：4

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