A 1 volt CMOS 2/4-level FSK digital demodulator for pager applications

被引:0
作者
Shakeri, K [1 ]
Hashemi, H [1 ]
Parsa, A [1 ]
Fotowat, A [1 ]
Rofougaran, R [1 ]
机构
[1] Sharif Univ Technol, Dept Elect Engn, Tehran, Iran
来源
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 2/4-level FSK digital demodulator for integration in a single multi-standard pager chip is presented The demodulator function is based on counting the zero crossings of the FSK signal. Frequency offset due to crystal imperfections, etc is corrected The output BER is 0.7% and 5% for input CNR of 4dB for 2-level and 4-level FSK respectively with frequency offset of 2kHz. This design uses 0.8-mu m CMOS technology and operates with power supply as low as 1 V.
引用
收藏
页码:219 / 222
页数:4
相关论文
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BUCHWALD A, 1998, ADV ENG COURS LAUS S
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GARDNER, FM .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1985, 33 (02) :131-138
[3]  
HARRISON TR, 1980, THESIS STANFORD U