Model, analyze, and simulate ΣΔ fractional-N frequency synthesizers -: Part 1

NOISE and speed are critical performance parameters for frequency synthesizers in communications systems. One of the more versatile synthesizer architectures is the Sigma Delta fractional-N circuit, which combines fast-switching speed, high resolution, and low phase noise. But to better understand how to apply such sources, techniques were developed at Philips Semiconductors (San Jose, CA) for the analysis and synthesis of Sigma Delta fractional-N synthesizers. Work was applied to various synthesizer configurations (MASH1, MASH11, and MASH11), and a set of mathematical expressions were developed to show the relation between the Sigma Delta sequence and Sigma Delta phase noise. Through analysis and simulation, it will be shown that the inherent nonlinearity of the voltage-controlled oscillator (VCO) in a fractional-N synthesizer, in conjunction with insufficiently suppressed Sigma Delta phase noise from the synthesizer, are causes of spurious generation in the synthesizer. In addition, gain mismatch of the charge pumps and other nonlinearities inside the synthesizer loop are major contributors to the phase-noise and spurious performance of a fractional-N frequency synthesizer.