Analyzing internal-switching induced simultaneous switching noise

被引：0

作者：

Yang, L ^{[1
]}

Yuan, JS ^{[1
]}

机构：

[1] Univ Cent Florida, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA

来源：

4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.

引用

页码：410 / 415

页数：6

共 12 条

[1]

BAKOGLU HB, 1990, CIRCUIT INTERCONNECT

[2]

CASIMIRO GG, 2000, P DEV CIRC SYST MAR

[3] Test generation for ground bounce in internal logic circuitry [J].

Chang, YS ;

Gupta, SK ;

Breuer, MA .

17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, :95-104

[4] Analysis of ground bounce in deep sub-micron circuits [J].

Chang, YS ;

Gupta, SK ;

Breuer, MA .

15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, :110-116

[5] New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design [J].

Eo, Y ;

Eisenstadt, WR ;

Jeong, JY ;

Kwon, OK .

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02) :303-312

[6] NOISE IN DIGITAL DYNAMIC CMOS CIRCUITS [J].

LARSSON, P ;

SVENSSON, C .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (06) :655-662

[7] Power supply noise in future IC's: A crystal ball reading [J].

Larsson, P .

PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1999, :467-474

[8] di/dt noise in CMOS integrated circuits [J].

Larsson, P .

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1997, 14 (1-2) :113-129

[9] ALPHA-POWER LAW MOSFET MODEL AND ITS APPLICATIONS TO CMOS INVERTER DELAY AND OTHER FORMULAS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) :584-594

[10]

SENTHINATHAN R, 1988, IEEE CUST IC C MAY

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