Low-voltage power-efficient adder design

被引：0

作者：

Margala, M ^{[1
]}

Alonzo, R ^{[1
]}

Chen, GQ ^{[1
]}

Jasionowski, BJ ^{[1
]}

Kraft, K ^{[1
]}

Lay, M ^{[1
]}

Lindner, J ^{[1
]}

Popovic, M ^{[1
]}

Suss, J ^{[1
]}

机构：

[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA

来源：

2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, CONFERENCE PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents results of a comprehensive comparative study of recently presented full-adder cells, examines their suitability in low-voltage low-power and high-performance applications and it proposes a design methodology for a low-voltage power-efficient full adder. The study and the methodology are based on a power supply range of 1.0V-1.8V in 0.18mum CMOS technology.

引用

页码：461 / 464

页数：4

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