Matching Discrete Signals for Hardware-in-the-Loop-Testing of PLCs

被引：0

作者：

Thonnessen, David ^{[1
]}

Rakel, Stefan ^{[1
]}

Reinker, Niklas ^{[1
]}

Kowalewski, Stefan ^{[1
]}

机构：

[1] Rhein Westfal TH Aachen, Informat Embedded Software 11, Aachen, Germany

来源：

IFAC PAPERSONLINE | 2018年 / 51卷 / 10期

关键词：

Validation; verification; testing; evaluation of embedded systems and applications; Programmable logic controllers; Process control; manufacturing;

D O I：

10.1016/j.ifacol.2018.06.267

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Executing Hardware-in-the-Loop (HiL) tests means to compare the actual behavior of a System Under Test (SUT) against a specification of its desired behavior, specified by the tester. The behavior of the SUT is available in form of time- and value-discrete signals coming from the SUT's I/O-modules. The HiL simulator compares these signals to reference signals, defined by the specification. Our approach performs this comparison by matching signal pairs, i.e. matching the actual and reference signal. We apply tolerances in order to allow the actual signal to deviate from the reference without causing the test to fail. (C) 2018, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

引用

页码：229 / 234

页数：6