Design of a Low Power 10-bit Cyclic D/A Converter with a Johnson Counter and a Capacitor Swapping Technique

A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35 mu m Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is 1MHz at a clock frequency of 2MHz. The power consumption is only 310 mu W at 3.3V power supply. The measured INL and DNL are within +/-0.7LSB and +/-0.75LSB, respectively.