Improved fabrication of fully-recessed normally-off SiN/SiO2/GaN MISFET based on the self-terminated gate recess etching technique

被引：8

作者：

Li, Mengjun ^{[1
]}

Wang, Jinyan ^{[1
]}

Zhang, Bin ^{[1
]}

Tao, Qianqian ^{[1
]}

Wang, Hongyue ^{[1
]}

Cao, Qirui ^{[1
]}

Huang, Chengyu ^{[1
]}

Liu, Jingqian ^{[1
]}

Mo, Jianghui ^{[2
]}

Wu, Wengang ^{[1
]}

Cai, Shujun ^{[2
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

[2] Hebei Semicond Res Inst, Shijiazhuang 050051, Hebei, Peoples R China

来源：

SOLID-STATE ELECTRONICS | 2021年 / 177卷

关键词：

GaN MISFET; Passivation; Fully-recess; Normally-off; Mask; ALGAN/GAN; QUALITY; MOSFET;

D O I：

10.1016/j.sse.2020.107927

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The thermal-oxidation/wet-etching gate-recess mask using low-pressure-chemical-vapor-deposition (LPCVD) SiN/atomic-layer-deposition (ALD) AlN combined with high-quality LPCVD-SiN/ALD-SiO2 gate dielectric has been developed for the fabrication of normally-off GaN MISFETs by the self-terminated gate recess etching technique. The experimental results showed that the SiN/AlN layer could effectively hinder the formation of surface oxide on GaN cap, and ALD grown SiO2 could effectively protect the GaN channel from high-temperature damages by the following LPCVD. As a result, the fabricated devices exhibit a small on-resistance degradation, 200 mV hysteresis @ Vth = 2.4 V, <1 nA/mm gate leakage current and 6 ? 108 on/off ratio.

引用

页数：5

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