共 26 条
[1]
2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications
[J].
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM),
2019,
[2]
Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations
[J].
JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS,
2010, 9 (04)
[4]
Baumgartner M, 2017, NAT NANOTECHNOL, V12, P980, DOI [10.1038/nnano.2017.151, 10.1038/NNANO.2017.151]
[8]
Donahue M, 1999, 6376 NISTIR