Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

被引：50
作者：
Tang, Xiyuan [1 ,2 ]
Liu, Jiaxin [3 ]
Shen, Yi [4 ,5 ]
Li, Shaolan [6 ]
Shen, Linxiao [2 ]
Sanyal, Arindam [7 ]
Ragab, Kareem [8 ]
Sun, Nan [9 ]
机构：
[1] Peking Univ, Inst Artificial Intelligence, Beijing 100871, Peoples R China
[2] Peking Univ, Sch Integrated Circuit, Beijing 100871, Peoples R China
[3] Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu 611731, Peoples R China
[4] Xidian Univ, Hangzhou Inst Technol, Hangzhou 311200, Peoples R China
[5] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
[6] Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA
[7] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA
[8] Broadcom Inc, Irvine, CA 92618 USA
[9] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2022年 / 69卷 / 06期
关键词：
Registers; Analog-digital conversion; Voltage; Clocks; Capacitors; Jitter; Bandwidth; Analog-to-digital converter (ADC); successive approximation register (SAR); low power; energy efficiency; NOISE-SHAPING SAR; DB SNDR; MU-W; 65-NM CMOS; 10-BIT; COMPARATOR; ENERGY; SPEED; REDUCTION; SFDR;
D O I：
10.1109/TCSI.2022.3166792
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.
引用
收藏
页码：2249 / 2262
页数：14
相关论文
共 108 条
  • [11] A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset
    Chae, Youngcheol
    Souri, Kamran
    Makinwa, Kofi A. A.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (12) : 3019 - 3027
  • [12] A 0.7-V 0.6-μW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction
    Chen, Long
    Tang, Xiyuan
    Sanyal, Arindam
    Yoon, Yeonam
    Cong, Jie
    Sun, Nan
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (05) : 1388 - 1398
  • [13] A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS
    Chen, Long
    Ragab, Kareem
    Tang, Xiyuan
    Song, Jeonggoo
    Sanyal, Arindam
    Sun, Nan
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (03) : 244 - 248
  • [14] Chen L, 2016, IEEE INT SYMP CIRC S, P2014, DOI 10.1109/ISCAS.2016.7538972
  • [15] Chen L, 2014, PROC EUR SOLID-STATE, P219, DOI 10.1109/ESSCIRC.2014.6942061
  • [16] A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
    Chen, Shuo-Wei Michael
    Brodersen, Robert W.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) : 2669 - 2680
  • [17] Chen Y.-P., 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers, P1, DOI DOI 10.1109/VLSIC.2014.6858431
  • [18] Chi-Hang Chan, 2012, 2012 IEEE Symposium on VLSI Circuits, P86, DOI 10.1109/VLSIC.2012.6243802
  • [19] Chun-Cheng Liu, 2010, 2010 IEEE International Solid-State Circuits Conference (ISSCC), P386, DOI 10.1109/ISSCC.2010.5433970
  • [20] On the jitter requirements of the sampling clock for analog-to-digital converters
    Da Dalt, N
    Harteneck, M
    Sandner, C
    Wiesbauer, A
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2002, 49 (09): : 1354 - 1360
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