Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

被引：50

作者：

Tang, Xiyuan ^{[1
,2
]}

Liu, Jiaxin ^{[3
]}

Shen, Yi ^{[4
,5
]}

Li, Shaolan ^{[6
]}

Shen, Linxiao ^{[2
]}

Sanyal, Arindam ^{[7
]}

Ragab, Kareem ^{[8
]}

Sun, Nan ^{[9
]}

机构：

[1] Peking Univ, Inst Artificial Intelligence, Beijing 100871, Peoples R China

[2] Peking Univ, Sch Integrated Circuit, Beijing 100871, Peoples R China

[3] Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu 611731, Peoples R China

[4] Xidian Univ, Hangzhou Inst Technol, Hangzhou 311200, Peoples R China

[5] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China

[6] Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA

[7] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA

[8] Broadcom Inc, Irvine, CA 92618 USA

[9] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2022年 / 69卷 / 06期

关键词：

Registers; Analog-digital conversion; Voltage; Clocks; Capacitors; Jitter; Bandwidth; Analog-to-digital converter (ADC); successive approximation register (SAR); low power; energy efficiency; NOISE-SHAPING SAR; DB SNDR; MU-W; 65-NM CMOS; 10-BIT; COMPARATOR; ENERGY; SPEED; REDUCTION; SFDR;

D O I：

10.1109/TCSI.2022.3166792

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

引用

页码：2249 / 2262

页数：14

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